The present invention relates to a nonvolatile semiconductor memory circuit. More particularly, it relates to an electrically erasable programmable read-only memory (EEPROM) circuit.
Recently, nonvolatile semiconductor memory circuits which electrically write or erase information have frequently been used since in these circuits it is unnecessary to use an ultraviolet ray, etc., which is a drawback. The principle of writing or erasing data involves the so-called "tunnel effect" in a thin film formed between a floating gate and a drain in a metal-oxide semiconductor (MOS) transistor. Further, a control gate is provided along with the floating gate which is coupled, via condenser or a capacitive coupling, to the control gate. A writing mode, a read-out mode, and an erase mode are set by changing the voltage level supplied to the control gate, the drain, etc. In such a case, the threshold voltage level of the MOS transistor varies depending on the voltage supplied to the control gate and to the drain, that is, the erase voltage and the write voltage.
Theoretically, in the reading operation the level of the voltage supplied to the control gate may be fixed at a zero voltage level, that is, at a non-biased state. However, when memory circuits are mass produced, the control gate voltage is inconveniently fixed. It is inconveniently fixed because, in the production process, each wafer varies on the outside or the inside, thereby causing the thickness of the thin film formed between the floating gate and the drain to vary and the length or the width of the channel to vary. Further, the fact that the electric source voltage varies after the memory circuits are produced must be taken into the consideration. However, such variation is not considered conventionally. This is a main draw back in the conventional memory circuits.
Further, conventional memory circuits have the following drawbacks:
(1) Enhancement-type MOS transistors must be used as bit gate transistors and as word control gate selection transistors since a bias voltage generated in the bias circuit is supplied at a decreasing value to the control gate of the MOS transistor during an erase operation and results in an erase error.
(2) A rapid read-out speed can not be obtained since enhancement-type MOS transistors are used.